Generic Motor Driver (GMD)
PROBLEM: PSAS has a need for brushed and brushles DC (BLDC) motor drivers in various power ranges from 0.5 to 2 kW. These are needed for on-board control servos as well as ground stations and antenna pointers. A scalable and configurable driver board must be created to meet as many motor driver needs as possible.
Requirements
- Layout for 3 half-bridges per board
- Must take 3 PWM inputs from GFE.
- Each PWM input shall drive one half-bridge
- Dead-time must be controlled on GMD board
- Must have separate, asynchronous enable input to turn off all drivers
- Must have 'watchdog' timer to disable all outputs if uC communication is lost
- Inputs must be electrically isolated
System Diagram:
Design
Features:
- Optically isolated inputs
- Re-programmable CPLD for dead-time control and failsafe logic
- 4 amp gate drivers
- Half bridges can be populated for 2 to 8 fets per bridge
Deadtime control
- Xilinx XC9572XL CPLD
- 40 MHz timebase clock
FET drivers
- Old standby part. Just works.
- IRF
- IRS2186SPBF
FETs
- 40 volts,
- 0.0019 ohm Rds ON
- IRF
- AUIRF7737L2TR
Input isolation
- Fairchild
- H11L1SM
Capacitors
Bus capacitance seems, at first glance, to be a nebulous subject on the web. Here are some thoughts on what sizes and values we should use.
Final choices, based on cost and reasonable assembly time:
- 10,880 uF total capacitance
- 16 Caps, 680uF each
- 0.5V ripple voltage, 50V max
- 50.56A ripple current, 3.16A each
- 0.001 ohms total, 0.016 ohms each
- 7000 hrs
- $0.5767 each (100 pc qtys)
- $9.227 per controller
- Digikey: P12402-ND
- Panasonic: EEU-FM1H681L
Schematic Diagram:
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Board Layout:
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Configurations
The configurations below describe the GMD as populated and programmed for the individual projects.
High current DC brush motor driver for Rocket Tracks
- Two half bridges available (U and V)
- All fets populated in each of the two half bridges (16 total)
- Two fet drivers populated
- 1.25 us dead time
- High current supply and output bus bars
- 24V supply voltage
- 50A supply current (@1.6HP)
- 1.2V ripple voltage limit (5% of 24V)
- Ripple current is 50A (assumes 0.024 ohm source impedance)
- Minimum required bus capacitance: 4,200uF
| Pin Number | Purpose |
|---|---|
| 1 | U-half bridge PWM input |
| 2 | V-half bridge PWM input |
| 4 | Watchdog input |
| 5 | Common (GND) |
| 6 | Enable input |
Connector Pins
The input connector pins described correspond to the 9 pin "serial" connector on the edge of the board opposite the FETs.
U-half bridge PWM input - When high, the high side FETs are active. When low, the low side FETs are active. Transitions from H-L and L-H are gated by the dead time controller. Note that there is no off-state associated with this pin. Either H or L side FETs will be active after the deadtime has passed.
V-half bridge PWM input - Same as U-half bridge PWM input.
Watchdog input - This input must be toggle from low to high or high to low at least once every 50 ms. If it is not toggled, all outputs (H and L) will turn OFF until the watchdog input is toggled again.
Common - This is the GND return for all of the inputs. Tied to battery negative net via 100k ohm resistor (to remove charge buildup between grounds).
Enable input - This input provides an asynchronous way for the control to disable all outputs. By using an asynchronous design, an on-board clock failure won't result in a runaway motor condition. When high, the system is enabled. When low or open circuit, the system is deactivated and all outputs (H and L) will turn OFF until the enable input is brought high again. This input can be series wired to both a control micro-controller and an emergency stop switch.
All inputs are designed for 3.3V to 5V logic.
Photos:
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